Semiconductor Structures Including Dielectric Layers and Capacitors Including Semiconductor Structures

ABSTRACT

Semiconductor structures including a first conductive layer; a dielectric layer on the first conductive layer; a second conductive layer on the dielectric layer; and a crystallized seed layer in at least one of a first portion between the first conductive layer and the dielectric layer and a second portion between the dielectric layer and the second conductive layer. Related capacitors and methods are also provided herein.

CLAIM OF PRIORITY

This application claims the benefit of Korean Patent Application No.10-2009-0101193, filed Oct. 23, 2009, the contents of which are herebyincorporated herein by reference as if set forth in its entirety.

FIELD

The present invention relates generally to semiconductor devices and,more particularly to, semiconductor structures including dielectriclayers, capacitors including semiconductor structures, and methods offorming semiconductor structures.

BACKGROUND

Dielectric layers used in semiconductor devices that are highlyintegrated and have a large capacity are typically very important.Dielectric layers may be provided between first and second conductivelayers of a capacitor. Dielectric layers may also be provided betweenfirst and second conductive layers functioning as an electrode or usedas a gate insulating layer. Furthermore, dielectric layers may be usedfor various purposes when semiconductor devices are fabricated.

For example, if a dielectric layer is provided between first and secondconductive layers of a capacitor, the dielectric layer typically has ahigh dielectric constant in order to increase the capacitance of thecapacitor. To increase the dielectric constant, the dielectric layer istypically crystallized. However, a high-temperature heat treatmentprocess may be required to crystallize the dielectric layer. Inaddition, when a capacitor including the dielectric layer is driven,some amount of charge may leak through the dielectric layer disposedbetween first and second conductive layers of the capacitor.

SUMMARY

Some embodiments of the present inventive concept provide asemiconductor structure including a first conductive layer; a dielectriclayer on the first conductive layer; a second conductive layer on thedielectric layer; and a crystallized seed layer in at least one of afirst portion between the first conductive layer and the dielectriclayer and a second portion between the dielectric layer and the secondconductive layer.

In further embodiments, the crystallized seed layer may be a niobiumlayer. The dielectric layer may be a tantalum oxide layer, a niobiumoxide layer, or a composite layer including a tantalum oxide layer and aniobium oxide layer. When oxidized, the crystallized seed layer may havethe same crystal structure as the dielectric layer.

In still further embodiments, the first conductive layer and the secondconductive layer may include a metal nitride layer, a noble metal layer,a noble metal oxide layer, a metal silicide layer, an impurity-dopedsilicon layer, or a metal layer. At least one of the first conductivelayer and the second conductive layer may be a metal nitride layer thathas the same crystal structure as the dielectric layer. The firstconductive layer or the second conductive layer may be a niobium nitridelayer or a tantalum nitride layer.

Some embodiments provide a semiconductor structure including a firstconductive layer including metal nitride; a dielectric layer on thefirst conductive layer including a tantalum oxide layer, a niobium oxidelayer, or a composite layer including a tantalum oxide layer and aniobium oxide layer; and a second conductive layer on the dielectriclayer including a metal nitride layer. A crystallized seed layer isformed in at least one of a first portion between the first conductivelayer and the dielectric layer and a second portion between thedielectric layer and the second conductive layer. The crystallized seedlayer includes a niobium layer.

Still further embodiments provide a capacitor including a firstconductive layer; a dielectric layer on the first conductive layer; asecond conductive layer on the dielectric layer; and a crystallized seedlayer in at least one of a first portion between the first conductivelayer and the dielectric layer and a second portion between thedielectric layer and the second conductive layer.

Some embodiments provide methods of forming a semiconductor structure,the method including forming a first conductive layer, forming adielectric layer on the first conductive layer; forming a secondconductive layer on the dielectric layer; and forming at least one of afirst crystallized seed layer on the first conductive layer and a secondcrystallized seed layer on the dielectric layer.

In further embodiments, a heat treatment process for crystallizing thedielectric layer may be performed after the first crystallized seedlayer, the dielectric layer, and the second crystallized seed layer aresequentially formed, or after the second conductive layer is formed. Thedielectric layer may be a tantalum oxide layer, a niobium oxide layer,or a composite layer including a tantalum oxide layer and a niobiumoxide layer. The crystallized seed layer may be a niobium layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-section of a semiconductor structure according to someembodiments of the present general inventive concept.

FIG. 2 is a cross-section of a semiconductor structure according to someembodiments of the present general inventive concept.

FIG. 3 is a cross-section of a semiconductor structure according to someembodiments of the present general inventive concept.

Figure is a flowchart illustrating processing steps in the fabricationof semiconductor structures illustrated in FIG. 1 and processing stepsfor heat treating a dielectric layer according to some embodiments ofthe present inventive concept.

FIG. 5 is a flowchart illustrating processing steps in the fabricationof semiconductor structures illustrated in FIG. 2 and processing stepsfor heat treating a dielectric layer according to some embodiments ofthe present inventive concept.

FIG. 6 is a flowchart illustrating processing steps in the fabricationof semiconductor structures illustrated in FIG. 1 and processing stepsfor heat treating a dielectric layer according to some embodiments ofthe present inventive concept.

FIG. 7 is a flowchart illustrating processing steps in the fabricationof semiconductor structures illustrated in FIG. 2 and processing stepsfor heat treating a dielectric layer according to some embodiments ofthe present inventive concept.

FIG. 8 is a flowchart illustrating processing steps in the fabricationof semiconductor structures illustrated in FIG. 3 and processing stepsfor heat treating a dielectric layer according to some embodiments ofthe present general inventive concept.

FIG. 9 is a graph illustrating X-ray peaks to illustrate a degree ofcrystallinity of a dielectric layer according to a heat treatmenttemperature in accordance with some embodiments of the present inventiveconcept.

FIG. 10 is a graph illustrating X-ray peaks to illustrate a degree ofcrystallinity of a dielectric layer according to a first conductivelayer at a constant heat treatment temperature in accordance with someembodiments.

FIG. 11 is a diagram of semiconductor devices including thesemiconductor structure illustrated in FIG. 3 in accordance with someembodiments of the present inventive concept.

FIG. 12 is a circuit diagram of a unit cell of a dynamic random accessmemory (DRAM) device including a capacitor according to some embodimentsof the present inventive concept.

FIG. 13 is a plan view of a memory module including a DRAM chip,according to some embodiments of the present inventive concept.

FIG. 14 is a block diagram of an electronic system including a DRAM chipaccording to some embodiments of the present inventive concept.

FIG. 15 is a block diagram of an electronic system including a logicchip according to some embodiments of the present inventive concept.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

The inventive concept now will be described more fully hereinafter withreference to the accompanying drawings, in which embodiments of theinvention are shown. This invention may, however, be embodied in manydifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the size and relative sizes of layers and regions may beexaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. As used herein, the term “and/or” includesany and all combinations of one or more of the associated listed itemsand may be abbreviated as “/”.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first signal could be termed asecond signal, and, similarly, a second signal could be termed a firstsignal without departing from the teachings of the disclosure.

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or“top,” may be used herein to describe one element's relationship toanother element as illustrated in the Figures. It will be understoodthat relative terms are intended to encompass different orientations ofthe device in addition to the orientation depicted in the Figures. Forexample, if the device in the Figures is turned over, elements describedas being on the “lower” side of other elements would then be oriented on“upper” sides of the other elements. The exemplary term “lower”, cantherefore, encompasses both an orientation of “lower” and “upper,”depending of the particular orientation of the figure. Similarly, if thedevice in one of the figures is turned over, elements described as“below” or “beneath” other elements would then be oriented “above” theother elements. The exemplary terms “below” or “beneath” can, therefore,encompass both an orientation of above and below.

Embodiments of the present inventive concept are described herein withreference to cross-section illustrations that are schematicillustrations of idealized embodiments of the present invention. Assuch, variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, embodiments of the present inventive concept should notbe construed as limited to the particular shapes of regions illustratedherein but are to include deviations in shapes that result, for example,from manufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a binarychange from implanted to non-implanted region. Likewise, a buried regionformed by implantation may result in some implantation in the regionbetween the buried region and the surface through which the implantationtakes place. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to illustrate the preciseshape of a region of a device and are not intended to limit the scope ofthe present invention.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” or “includes” and/or “including” when used in thisspecification, specify the presence of stated features, regions,integers, steps, operations, elements, and/or components, but do notpreclude the presence or addition of one or more other features,regions, integers, steps, operations, elements, components, and/orgroups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and/orthe present application, and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

Semiconductor structures according to some embodiments of the presentinventive concept includes first and second, for example, top andbottom, conductive layers, a dielectric layer, and a crystallized seedlayer, wherein the dielectric layer and the crystallized seed layer areprovided between the first and second conductive layers. Thecrystallized seed layer may be formed on, under, or both on and underthe dielectric layer. In some embodiments, the dielectric layer may be,for example, a tantalum oxide layer, a niobium oxide layer, or acomposite layer including a tantalum oxide layer and a niobium oxidelayer. The tantalum oxide layer may be represented by Ta₂O₅ or TaO. Theniobium oxide layer may be represented by Nb₂O₅ or NbO. The crystallizedseed layer may be a niobium layer.

Semiconductor structures according to some embodiments may be used as,for example, a capacitor. The capacitor may be used in a semiconductordevice, such as a dynamic random access memory (DRAM) device, a logicdevice, or the like. Various embodiments of the present generalinventive concept will be discussed below with respect to FIGS. 1through 15.

Various semiconductor structures will now be discussed in accordancewith embodiments of the inventive concept with respect to FIGS. 1through 3. Referring first to FIG. 1, a cross-section of semiconductorstructure 200 in accordance with some embodiments of the present generalinventive concept will be discussed. As illustrated in FIG. 1, thesemiconductor structure 200 according includes a first conductive layer100. The first conductive layer 100 may be any material layer havingconductivity without departing from the scope of embodiments discussedherein. Thus, the first conductive layer 100 may be, for example, ametal nitride layer, a noble metal layer, a noble metal oxide layer, ametal silicide layer, an impurity-doped silicon layer, or a metal layer.

Examples of the metal nitride layer include a titanium nitride (TiN)layer, a tantalum nitride (TaN) layer, a niobium nitride (NbN) layer, atungsten nitride (WN) layer, a titanium aluminum nitride (TiAlN) layer,a titanium silicon nitride (TiSiN) layer, a vanadium nitride (VN) layer,and a molybdium nitride (MoN) layer. Examples of the noble metal layerinclude a ruthenium layer Ru and a platinum layer Pt. Examples of thenoble metal oxide layer include a ruthenium oxide layer and an iridiumoxide layer. Examples of the metal silicide layer include a titaniumsilicide layer, a tungsten silicide layer, and a cobalt silicide layer.Examples of the metal layer include an aluminum layer, and a copperlayer. However, the metal nitride layer, the noble metal layer, thenoble metal oxide layer, the metal silicide layer, and the metal layerare not limited to the above examples.

A first crystallized seed layer 110 and a dielectric layer 120 may besequentially provided on the first conductive layer 100. The firstcrystallized seed layer 110 may be formed in a first portion between thefirst conductive layer 100 and the dielectric layer 120. The firstcrystallized seed layer 110 may function as a seed for helpingcrystallization of the dielectric layer 120 of the semiconductorstructure 200 when the dielectric layer 120 is heat treated. The firstcrystallized seed layer 110 may lower the crystallization temperature ofthe dielectric layer 120 in order to increase the dielectric constant ofthe dielectric layer 120. The dielectric layer 120 may be a tantalumoxide layer, a niobium oxide layer, or a composite layer including atantalum oxide layer and a niobium oxide layer. When the crystallizationtemperature of the dielectric layer 120 is decreased, the dielectricconstant of the dielectric layer 120 may be increased to 60 or more.When the dielectric layer 120 is a tantalum oxide layer, a niobium oxidelayer, or a composite layer including a tantalum oxide layer and aniobium oxide layer, the dielectric layer 120 has a hexagonal crystalstructure.

The first crystallized seed layer 110 may be a material layer that has acrystal structure similar to that of the dielectric layer 120 whenoxidized to lower the crystallization temperature of the dielectriclayer 120. For example, the first crystallized seed layer 110 may be amaterial layer having a hexagonal crystal structure, such as a niobiumlayer.

A second conductive layer 140 may be provided on the dielectric layer120. The second conductive layer 140 and the first conductive layer 100may include the same material. At least one of the first conductivelayer 100 and the second conductive layer 140 may be a metal nitridelayer having the same crystal structure as that of the dielectric layer120 in order to increase the dielectric constant of the dielectric layer120. For example, at least one of the first conductive layer 100 and thesecond conductive layer 140 may be a tantalum nitride layer (TaN) or aniobium nitride layer (NbN).

In some embodiments, the first conductive layer 100, the firstcrystallized seed layer 110, the dielectric layer 120, and the secondconductive layer 140 may form a capacitor. The first crystallized seedlayer 110 may be partially included in the dielectric layer 120 when thedielectric layer 120 is heat treated in the subsequent process.

Referring now to FIG. 2, a cross-section of a semiconductor structure200 a according to some embodiments of the present general inventiveconcept will be discussed. As illustrated in FIG. 2, the semiconductorstructure 200 a is similar to the semiconductor structure 200 of FIG. 1,except that the first crystallized seed layer 110 is not formed on thefirst conductive layer 100. Instead, a second crystallized seed layer130 is formed on the dielectric layer 120.

The semiconductor structure 200 a illustrated in FIG. 2 includes a firstconductive layer 100 and a dielectric layer 120. The first conductivelayer 100 and the dielectric layer 120 have been described withreference to the semiconductor structure 200 of FIG. 1.

The second crystallized seed layer 130 and a second conductive layer 140may be sequentially provided on the dielectric layer 120. The secondcrystallized seed layer 130 may be provided in a second portion betweenthe second conductive layer 140 and the dielectric layer 120. The secondcrystallized seed layer 130 may function as a seed for helpingcrystallization of the dielectric layer 120 of the semiconductorstructure 200 a when the dielectric layer 120 is heat treated. Thesecond crystallized seed layer 130 may contribute to decreasing thecrystallization temperature of the dielectric layer 120 and increasingthe dielectric constant of the dielectric layer 120. The dielectricconstant of the dielectric layer 120 may be increased to 60 or more whenthe dielectric layer 120 is crystallized. The second crystallized seedlayer 130 may be a material layer that has the same crystal structure asthat of the dielectric layer 120 when oxidized to lower thecrystallization temperature of the dielectric layer 120.

The second crystallized seed layer 130 may include a similar material asthat of the first crystallized seed layer 110 of the semiconductorstructure 200 illustrated in FIG. 1. For example, the secondcrystallized seed layer 130 may be a niobium layer. The secondconductive layer 140 in the semiconductor structure 200 a is the same asthe second conductive layer 140 of the semiconductor structure 200.

In some embodiments, the first conductive layer 100, the dielectriclayer 120, the second crystallized seed layer 130, and the secondconductive layer 140 may form a capacitor. The second crystallized seedlayer 130 may be partially included in the dielectric layer 120 when thedielectric layer 120 is heat treated in the subsequent process.

Referring now to FIG. 3, a cross-section of a semiconductor structure200 b according to some embodiments of the present general inventiveconcept will be discussed. As illustrated in FIG. 3, the semiconductorstructure 200 b has features of the semiconductor structure 200 and thesemiconductor structure 200 a. In other words, the semiconductorstructure 200 b illustrated in FIG. 3 is similar to the semiconductorstructures 200 and 200 a, except that the first crystallized seed layer110 is formed on the first conductive layer 100, and the secondcrystallized seed layer 130 is formed on the dielectric layer 120.

The semiconductor structure 200 b may include a first conductive layer100. The first conductive layer 100 of the semiconductor structure 200 bis similar to the first conductive layer 100 of the semiconductorstructure 200. A first crystallized seed layer 110 may be provided onthe first conductive layer 100. The first crystallized seed layer 110may be provided on a first portion between the first conductive layer100 and a dielectric layer 120. The first crystallized seed layer 110 ofthe semiconductor structure 200 b is similar to the crystallized seedlayer 110 of the semiconductor structure 200.

The dielectric layer 120 is provided on the first crystallized seedlayer 110. The dielectric layer 120 is similar to the dielectric layers120 of the semiconductor structures 200 and 200 a. A second crystallizedseed layer 130 and a second conductive layer 140 are sequentiallyprovided on the dielectric layer 120. The second crystallized seed layer130 is provided on a second portion between the second conductive layer140 and the dielectric layer 120. The second crystallized seed layer 130and the second conductive layer 140 are respectively similar to thesecond crystallized seed layer 130 and the second conductive layer 140of the semiconductor structure 200 a.

In some embodiments, the first conductive layer 100, the firstcrystallized seed layer 110, the dielectric layer 120, the secondcrystallized seed layer 130, and the second conductive layer 140 mayform a capacitor. Each of the first crystallized seed layer 110 andsecond crystallized seed layer 130 may be partially included in thedielectric layer 120 when the dielectric layer 120 is heat treated inthe subsequent process.

Various processing steps in the fabrication of semiconductor structuresand processing steps for heat treating a dielectric layer will now bediscussed with respect to FIGS. 4 through 8. These embodiments may beperformed individually or in combination without departing from thescope of embodiments discussed herein.

Referring first to FIG. 4, a flowchart illustrating processing steps inthe fabrication of semiconductor structures illustrated in FIG. 1 andprocessing steps for heat treating a dielectric layer in accordance withsome embodiments of the inventive concept will be discussed. Asillustrated in FIG. 4, operations begin by forming a first conductivelayer 100 of the semiconductor structure 200 illustrated in FIG. 1(block 300). The first conductive layer 100 may be any of the materiallayers that have been described with reference to the semiconductorstructures 200, 200 a, and 200 b illustrated in FIGS. 1 through 3. Thefirst conductive layer 100 may be formed by sputtering, chemical vapordeposition (CVD), or atomic layer deposition (ALD).

The first crystallized seed layer 110 illustrated in FIG. 1 is formed onthe first conductive layer 100 (block 302). The first crystallized seedlayer 110 may be a niobium layer, as discussed above with reference tothe semiconductor structure 200 of FIG. 1. The first crystallized seedlayer 110 may be formed by sputtering, CVD, or ALD. The firstcrystallized seed layer 110 may have a thickness of about 10 throughabout 100 Å.

In some embodiments, the first crystallized seed layer 110 may be aniobium layer. The niobium layer may be formed by performing CVD using aprecursor compound containing niobium. The precursor compound containingniobium may be an alkoxide precursor compound such as Nb(OMe)₅,Nb(OEt)₅, or Nb(OBu)₅, Nb[N CH₃ ₂]₅; or an amide precursor compound suchas Nb[N(CH₃)₂]₅, (NtBu)Nb(NEtMe)₃, or (NtBu)Nb(NEt₂)₂ where Merepresents methyl, Et represents ethyl, and Bu represents butyl.

The dielectric layer 120 is formed on the first crystallized seed layer110 as illustrated in FIG. 1 (block 304). The dielectric layer 120 maybe any of the material layers that have been discussed above withreference to the semiconductor structure 200 of FIG. 1. The dielectriclayer 120 may be formed by sputtering, CVD, or ALD.

After the first crystallized seed layer 110 and the dielectric layer 120are formed, the dielectric layer 120 is heat treated to be crystallized(block 306). The heat treatment process may be a furnace heat treatmentprocess, a rapid heat treatment process, an ultraviolet heat treatmentprocess, or a plasma heat treatment process, and may be performed underan oxygen, nitrogen, or air atmosphere. During the heat treatmentprocess for the dielectric layer 120, the first crystallized seed layer110 helps crystallization of the dielectric layer 120. Thus, due to thefirst crystallized seed layer 110, the heat treatment process for thedielectric layer 120 may be performed at a low temperature, for example,a temperature of about 575° C. When the dielectric layer 120 is heattreated, the first crystallized seed layer 110 may be partially includedin the dielectric layer 120.

After the heat treatment process for the dielectric layer 120 isperformed, the second conductive layer 140 is formed on the dielectriclayer 120 as illustrated in FIG. 1 (block 308). The second conductivelayer 140 may be any of the material layers that have been discussedabove with reference to the semiconductor structure 200 of FIG. 1. Thesecond conductive layer 140 may be formed by sputtering, CVD, or ALD.

Subsequently, if needed, the dielectric layer 120 may be further heattreated after the second conductive layer 140 is formed (this operationis not shown). If the dielectric layer 120 is further heat treated, thedielectric layer 120 may be further crystallized.

Referring now to FIG. 5, a flowchart illustrating processing steps inthe fabrication of semiconductor structures illustrated in FIG. 2 andprocessing steps of heat treating a dielectric layer according to someembodiments of the present inventive concept. As illustrated in FIG. 5,the method is similar to details discussed above with respect to FIG. 4,except that the first crystallized seed layer 110 is not formed on thefirst conductive layer 100, and the second crystallized seed layer 130is formed on the dielectric layer 120 and then the dielectric layer 120is heat treated.

For example, the first conductive layer 100 of the semiconductorstructure 200 a illustrated in FIG. 2 is formed (block 300). The firstconductive layer 100 may be the same material layer as discussed abovewith respect to FIG. 4, and may be formed using the similar methods.

The dielectric layer 120 is formed on the first conductive layer 100 asillustrated in FIG. 2 (block 400). The dielectric layer 120 may be anyof the material layers that have been discussed above with reference tothe semiconductor structure 200 of FIG. 2. The dielectric layer 120 maybe formed by sputtering, CVD, or ALD.

The second crystallized seed layer 130 is formed on the dielectric layer120 (block 402). The second crystallized seed layer 130 may be a niobiumlayer as discussed above with reference to the semiconductor structure200 of FIG. 2. The second crystallized seed layer 130 and the firstcrystallized seed layer 110 may be formed of the same material. If thesecond crystallized seed layer 130 is a niobium layer, the precursorsdescribed above may be used. The second crystallized seed layer 130 maybe formed by sputtering, CVD, or ALD. The second crystallized seed layer130 may be formed to a thickness of 10 through 100 Å.

After the dielectric layer 120 and the second crystallized seed layer130 are formed, the dielectric layer 120 is heat treated to becrystallized (block 306). Similar to embodiments discussed above, theheat treatment process may be a furnace heat treatment process, a rapidheat treatment process, an ultraviolet heat treatment process, or aplasma heat treatment process, and may be performed under an oxygen,nitrogen, or air atmosphere. During the heat treatment process for thedielectric layer 120, the second crystallized seed layer 130 helpscrystallization of the dielectric layer 120. Thus, due to the secondcrystallized seed layer 130, the heat treatment process for thedielectric layer 120 may be performed at a low temperature, for example,a temperature of about 575° C. When the dielectric layer 120 is heattreated, the second crystallized seed layer 130 may be partiallyincluded in the dielectric layer 120.

After the heat treatment process for the dielectric layer 120 isperformed, the second conductive layer 140 is formed on the secondcrystallized seed layer 130 as illustrated in FIG. 2 (block 308). Thesecond conductive layer 140 may be any of the material layers that havebeen discussed above with reference to the semiconductor structure 200 aof FIG. 2. The second conductive layer 140 may be formed using thesimilar methods.

Subsequently, if needed, the dielectric layer 120 may be further heattreated after the second conductive layer 140 is formed (not shown). Ifthe dielectric layer 120 is further heat treated, the dielectric layer120 may be further crystallized.

Referring now to FIG. 6, a flowchart illustrating processing steps inthe fabrication of semiconductor structures of FIG. 1 and processingsteps in heat treating a dielectric layer according to some embodimentof the present inventive concept. As illustrated in FIG. 6, the methodsillustrated in FIG. 6 are similar to those discussed above with respectto FIG. 4, except that the dielectric layer 120 is heat treated afterthe second conductive layer 140 is formed on the dielectric layer 120.

For example, as discussed above with respect to the semiconductorstructure 200 of FIG. 1 and the methods according embodiments discussedabove, the first conductive layer 100, the first crystallized seed layer110, and the dielectric layer 120 are sequentially formed on the firstlayer (blocks 300, 302, and 304). The first conductive layer 100, thefirst crystallized seed layer 110, and the dielectric layer 120 may beany of the material layers and may be formed using the methods discussedabove.

As illustrated in the semiconductor structure 200 of FIG. 1, the secondconductive layer 140 is formed on the dielectric layer 120 (block 308).The second conductive layer 140 may be any of the material layersdescribed in the first and second embodiments and may be performed usingthe methods described in the first and second embodiments.

After the first crystallized seed layer 110, the dielectric layer 120,and the second conductive layer 140 are formed, the dielectric layer 120is heat treated to be crystallized (block 306). Similar to embodimentsdiscussed above, the heat treatment process may be a furnace heattreatment process, a rapid heat treatment process, an ultraviolet heattreatment process, or a plasma heat treatment process, and may beperformed under an oxygen, nitrogen, or air atmosphere. During the heattreatment process for the dielectric layer 120, the first crystallizedseed layer 110 helps crystallization of the dielectric layer 120. Thus,due to the first crystallized seed layer 110, the heat treatment processfor the dielectric layer 120 may be performed at a low temperature, forexample, a temperature of about 575° C. When the dielectric layer 120 isheat treated, the first crystallized seed layer 110 may be partiallyincluded in the dielectric layer 120.

Referring now to FIG. 7, a flowchart illustrating processing steps inthe fabrication of the semiconductor structure illustrated in FIG. 2 andprocessing steps for heat treating a dielectric layer according to someembodiments of the present general inventive concept will be discussed.As illustrated in FIG. 7, the method of forming the semiconductorstructure of FIG. 2 and the method of heat treating a dielectric layerof FIG. 7 is similar to the methods discussed above with respect to thesemiconductor structure of FIG. 2, except that the dielectric layer 120is heat treated after the second conductive layer 140 is formed on thedielectric layer 120.

For example, as discussed above with reference to the semiconductorstructure 200 a of FIG. 2 and related methods, the first conductivelayer 100, the dielectric layer 120, and the second crystallized seedlayer 130 may be sequentially formed on a first layer (blocks 300, 400,and 402). The first conductive layer 100, the dielectric layer 120, andthe second crystallized seed layer 130 may include the material layerdiscussed above and may be formed using the methods described.

As illustrated with reference to the semiconductor structure 200 a ofFIG. 2, the second conductive layer 140 is formed on the secondcrystallized seed layer (block 404). The second conductive layer 140 maybe any of the material layers discussed above and may be formed usingthe related methods.

After the dielectric layer 120, the second crystallized seed layer 130,and the second conductive layer 140 are formed, the dielectric layer 120is heat treated to be crystallized (block 306). Similar to embodimentsdiscussed above, the heat treatment process may be a furnace heattreatment process, a rapid heat treatment process, an ultraviolet heattreatment process, or a plasma heat treatment process, and may beperformed under an oxygen, nitrogen, or air atmosphere. During the heattreatment process for the dielectric layer 120, the second crystallizedseed layer 130 helps crystallization of the dielectric layer 120. Thus,due to the second crystallized seed layer 130, the heat treatmentprocess for the dielectric layer 120 may be performed at a lowtemperature, for example, a temperature of about 575° C. When thedielectric layer 120 is heat treated, the second crystallized seed layer130 may be partially included in the dielectric layer 120.

Referring now to FIG. 8, a flowchart illustrating processing steps inthe fabrication of semiconductor structures illustrated in FIG. 3 andprocessing steps for heat treating a dielectric layer according to someembodiments of the inventive concept will be discussed. As illustratedin FIG. 8, the method of forming the semiconductor structure of FIG. 3and a method of heat treating a dielectric layer may be similar to theembodiments discussed above, except that the dielectric layer 120 isheat treated after the first crystallized seed layer 110 is formed andthen the second crystallized seed layer 130 is formed on the dielectriclayer 120. Thus, embodiments illustrated in FIG. 8 are a combination ofdifferent embodiments discussed above.

For example, as discussed above with reference to the semiconductorstructures 200 and 200 b of FIGS. 1 and 3, the first conductive layer100, the first crystallized seed layer 110, and the dielectric layer 120may be sequentially formed on a first layer (blocks 300, 302, 304). Thefirst conductive layer 100, the first crystallized seed layer 110, andthe dielectric layer 120 may be any of the material layers discussedwith respect to embodiments above and may be formed using the relatedmethods.

As illustrated in the semiconductor structures 200 a and 200 b of FIGS.2 and 3, the second crystallized seed layer 130 is formed on thedielectric layer 120 (block 402). The second crystallized seed layer 130may be any of the material layers discussed above and may be formedusing the related methods.

After the first crystallized seed layer 110, the dielectric layer 120,and the second crystallized seed layer 130 are formed, the dielectriclayer 120 is heat treated to be crystallized (block 306). The dielectriclayer 120 may be heat treated using the same method as described in thefirst through fourth embodiments. During the heat treatment process forthe dielectric layer 120, the first crystallized seed layer 110 and thesecond crystallized seed layer 130 help crystallization of thedielectric layer 120. Thus, due to the first crystallized seed layer 110and the second crystallized seed layer 130, the heat treatment processfor the dielectric layer 120 may be performed at a low temperature, forexample, a temperature of about 575° C. When the dielectric layer 120 isheat treated, the first crystallized seed layer 110 and the secondcrystallized seed layer 130 may be partially included in the dielectriclayer 120.

After the dielectric layer 120 is heat treated, as illustrated in FIGS.2 and 3, the second conductive layer 140 is formed on the secondcrystallized seed layer 130 (block 308). The second conductive layer 140may be any of the material layers described with reference to thesemiconductor structures 200 a and 200 b of FIGS. 2 and 3. The secondconductive layer 140 may be formed using the methods described withrespect to embodiments discussed above.

Subsequently, after the second conductive layer 140 is formed, thedielectric layer 120 is further heat treated (block 306 a). Theoperations of block 306 a may be the same as the operations of block306. By performing the operations of block 306 a, the dielectric layer120 may be further crystallized.

A degree of crystallinity of a dielectric layer according to the heattreatment temperature for the dielectric layer in accordance with someembodiments will now be discussed. Referring first to FIG. 9, a graphshowing X-ray peaks to illustrate a degree of crystallinity of adielectric layer according to a heat treatment temperature for thedielectric layer in accordance with some embodiments will be discussed.As illustrated in FIG. 9, the graph shows X-ray peaks obtained byirradiating X rays onto samples obtained by forming a niobium nitridelayer, a niobium layer, and a tantalum oxide layer on a siliconsubstrate and then heat treating the tantalum oxide layer at varioustemperatures. That is, the silicon substrate is used as a first layer,the niobium nitride layer is used as a first conductive layer, theniobium layer is used as a first crystallized seed layer, and thetantalum oxide layer is used as a dielectric layer.

The heat treatment for the dielectric layer may be a rapid heattreatment process. X-rays are irradiated to a sample (Asdepo) includingthe tantalum oxide layer that is not heat treated, a sample (RTA 550)including the tantalum oxide layer that is rapidly heat treated at atemperature of 550° C., a sample (RTA 575) including the tantalum oxidelayer that is rapidly heat treated at a temperature of 575° C., and asample (RTA 600) including the tantalum oxide layer that is rapidly heattreated at a temperature of 600° C.

A tantalum oxide layer having a hexagonal crystal structure has an X-raypeak at around 22.5° C. Referring to FIG. 9, the sample including thetantalum oxide layer that is rapidly heat treated at a temperature of575° C. has an X-ray peak at around 22.5° C. The sample including thetantalum oxide layer that is rapidly heat treated at a temperature of600° C. also has an X-ray peak at around 22.5° C. Althoughconventionally a tantalum oxide layer having a hexagonal crystalstructure has an X-ray peak at around 22.5° C. at a temperature of 700°C. or higher, the samples according to embodiments of the presentinventive concept have the X-ray peak of the tantalum oxide layer havinga hexagonal crystal structure at a temperature lower than 700° C., forexample, 575° C. Thus, it can be seen that the heat treatment processcan be performed at a relatively low temperature.

Referring now to FIG. 10, a graph showing X-ray peaks to illustrate adegree of crystallinity of a dielectric layer according to a firstconductive layer at a constant heat treatment temperature in accordancewith some embodiments will be discussed. In particular, FIG. 10illustrates a graph showing X-ray peaks obtained by irradiating X raysonto samples obtained by forming either a titanium nitride layer orniobium nitride layer, a niobium layer, and a tantalum oxide layer on asilicon substrate and then heat treating the tantalum oxide layer at atemperature of 600° C. That is, the silicon substrate is used as a firstlayer, the titanium nitride layer or the niobium nitride layer is usedas a first conductive layer, the niobium layer is used as a firstcrystallized seed layer, and the tantalum oxide layer is used as adielectric layer. The heat treatment for the dielectric layer may be arapid heat treatment process.

Referring to FIG. 10, X-ray peaks at around 22.5° C. and around 34° C.are observed. As described above, in general, a tantalum oxide layerhaving a hexagonal crystal structure has an X-ray peak at around 22.5°C. When the first conductive layer is a niobium nitride layer, the X-raypeak appears at around 22.5° C., and when the first conductive layer isa titanium nitride layer, the X-ray peak appears at around 34° C. Thus,it can be seen that when the dielectric layer is heat treated at atemperature of 600° C., the X-ray peak of the tantalum oxide layerhaving a hexagonal crystal structure is clearly observed, and variesaccording to a first conductive layer. The variance in location of theX-ray peak indicates the tantalum oxide layer has various degrees ofcrystallinity.

Semiconductor devices including semiconductor structures in accordancewith some embodiments will now be discussed. Referring now to FIG. 11, asemiconductor device 600 including the semiconductor structure 200 b ofFIG. 3 in accordance with some embodiments of the present generalinventive concept will be discussed. As illustrated, the semiconductordevice 600 of FIG. 11 includes the semiconductor structure 200 b of FIG.3. However, the semiconductor structures 200 and 200 a may also beincluded in the semiconductor device 600 without departing from thescope of the present inventive concept.

The semiconductor device 600 includes an impurity region 515 in asemiconductor substrate 510, for example, a silicon substrate. Theimpurity region 515 may be a p-type impurity region or n-type impurityregion, according to a conductivity type of the silicon substrate. Aninsulating layer 530, for example, a silicon oxide layer may be formedon the semiconductor substrate 510. Contact holes 520 and 535 maycontact the semiconductor substrate 510 and may be formed in theinsulating layer 530. A conductive plug 525 may fill the contact hole520. The conductive plug 525 may include various conductive materials,for example, tungsten, an impurity-doped polysilicon, aluminum, orcopper.

The semiconductor structure 200 b may fill the contact hole 535 and onthe insulating layer 530. The semiconductor structure 200 b may be acapacitor. The first conductive layer 100 may be formed on an inner wallof the contact hole 535. The first crystallized seed layer 110, thedielectric layer 120, the second crystallized seed layer 130, and thesecond conductive layer 140 may be sequentially formed on the firstconductive layer 100. The first crystallized seed layer 110, thedielectric layer 120, the second crystallized seed layer 130, the secondconductive layer 140, and the first conductive layer 100 may be any ofthe material layers that have been described in the previousembodiments. The semiconductor structure 200 b may also be used in otherportions of the semiconductor device 600 of FIG. 1.

Example uses of embodiments discussed herein will now be discussed withrespect to FIGS. 12 through 15. The semiconductor structures 200, 200 a,and 200 b may be used as a capacitor. Such a capacitor may be used in asemiconductor device, for example, a dynamic random access memory (DRAM)device, or a logic device. Referring first to FIG. 12, a diagramillustrating the semiconductor structure 200 used as a capacitor will bediscussed. As illustrated, FIG. 12 is a circuit diagram of a unit cellof a DRAM device including a capacitor according to some embodiments ofthe present general inventive concept. Although a unit cell of a DRAMdevice may have various structures, the unit cell according toembodiments illustrated in FIG. 12 includes a transistor 710 and acapacitor 730. The transistor 710 is connected to a word line 730. Thetransistor includes a source region and a drain region. The bit line 750is connected to either the source region or the drain region. Theunconnected region among the source region and the drain region isconnected to the semiconductor structure 200. That is, semiconductorstructures according to some embodiments of the present generalinventive concept are used as a capacitor of a DRAM device.

A semiconductor device according to some embodiments of the presentgeneral inventive concept, for example, a DRAM device or a logic devicemay be variously used. When the semiconductor device according to someembodiments, for example, a DRAM device or a logic device is packaged, aDRAM chip or a logic chip is obtained. The DRAM chip and the logic chipmay be used in various applications, some of which will be described indetail herein.

Referring now to FIG. 13, a plan view of a memory module 800 including aDRAM chip according to some embodiments of the present general inventiveconcept will be discussed. As illustrated in FIG. 13, DRAM chips 50-58are obtained by packaging semiconductor devices according to embodimentsof the present invention. The DRAM chips 50-58 may be used in the memorymodule 800. In the memory module 800, the DRAM chips 50-58 may beattached to a module substrate 801. In the memory module 800, aconnection portion 802 is located on one side of the module substrate801 and is inserted into a socket of a mother board, and a ceramicdecoupling capacitor 59 is disposed on the module substrate 801. Thestructure of the memory module 800 may not be limited to FIG. 13.

Referring now to FIG. 14, a block diagram of an electronic system 900including a DRAM chip according to some embodiments of the presentgeneral inventive concept will be discussed. As illustrated in FIG. 14,the electronic system 900 according to some embodiments may be acomputer. The electronic system 900 includes a central processing unit(CPU) 905; a peripheral device such as a floppy disc drive 907 or a CDROM drive 909; input and output devices 908 and 910, a DRAM chip 912,and a read only memory (ROM) chip 914. These components send or receivecontrol signals or data by using a communication channel 911. The DRAMchip 912 may be replaced with the memory module 800 including the DRAMchips 50-58 illustrated in FIG. 13.

Referring now to FIG. 15, a block diagram of an electronic system 1000including a logic chip according to some embodiment of the presentgeneral inventive concept will be discussed. Referring to FIG. 15, theelectronic system 1000 may include a processor 930, an input/outputdevice 950, and a logic chip 940, which data-communicate with each otherby a bus 960. The processor 930 performs a program and controls theelectronic system 1000. The input/output device 950 may be used to inputor output data of the electronic system 1000. The electronic system 1000may be connected to an external device, such as a personal computer ornetwork through the input/output device 950 and may exchange data withthe external device. The logic chip 940 may process cords and data foroperating the processor 310.

The electronic system 1000 may be used in various electronic controldevice requiring the logic chip 940, for example, in mobile phones, MP3players, navigation devices, solid state disks (SSD), and householdappliances.

Semiconductor structures according to embodiments discussed above mayinclude a dielectric layer on, under, or on and under a crystallizedseed layer. The dielectric layer may be a tantalum oxide layer, aniobium oxide layer, or a composite layer including a tantalum oxidelayer and a niobium oxide layer. The crystallized seed layer may be aniobium layer. Due to the crystallized seed layer, the dielectric layermay be crystallized by a low-temperature heat treatment. When thedielectric layer is crystallized by low-temperature heat treatment, thedielectric constant of the dielectric layer may be increased and leakagecharacteristics of the dielectric layer may be improved.

While the inventive concept has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodthat various changes in form and details may be made therein withoutdeparting from the spirit and scope of the following claims.

1. A semiconductor structure comprising: a first conductive layer; adielectric layer on the first conductive layer; a second conductivelayer on the dielectric layer; and a crystallized seed layer in at leastone of a first portion of the semiconductor structure between the firstconductive layer and the dielectric layer and a second portion of thesemiconductor structure between the dielectric layer and the secondconductive layer.
 2. The semiconductor structure of claim 1, wherein thecrystallized seed layer comprises a niobium layer.
 3. The semiconductorstructure of claim 1, wherein the dielectric layer comprises one of atantalum oxide layer, a niobium oxide layer and a composite layerincluding a tantalum oxide layer and a niobium oxide layer.
 4. Thesemiconductor structure of claim 1, wherein when oxidized, thecrystallized seed layer has a similar crystal structure to a crystalstructure of the dielectric layer.
 5. The semiconductor structure ofclaim 4, wherein the crystallized seed layer comprises a niobium layerand wherein the dielectric layer comprises one of a tantalum oxidelayer, a niobium oxide layer and a composite layer comprising a tantalumoxide layer and a niobium oxide layer.
 6. The semiconductor structure ofclaim 1, wherein each of the first conductive layer and the secondconductive layer comprises at least one of a metal nitride layer, anoble metal layer, a noble metal oxide layer, a metal silicide layer, animpurity-doped silicon layer and a metal layer.
 7. The semiconductorstructure of claim 1, wherein at least one of the first conductive layerand the second conductive layer is a metal nitride layer that has asimilar crystal structure as a crystal structure of the dielectriclayer.
 8. The semiconductor structure of claim 7, wherein one of thefirst conductive layer and the second conductive layer is a niobiumnitride layer or a tantalum nitride layer.
 9. A semiconductor structurecomprising: a first conductive layer that includes metal nitride; adielectric layer on the first conductive layer, wherein the dielectriclayer is one of a tantalum oxide layer, a niobium oxide layer and acomposite layer including a tantalum oxide layer and a niobium oxidelayer; a second conductive layer on the dielectric layer, wherein thesecond conductive layer is a metal nitride layer; and a crystallizedseed layer including niobium and is in at least one of a first portionof the semiconductor structure between the first conductive layer andthe dielectric layer, and a second portion of the semiconductorstructure between the dielectric layer and the second conductive layer.10. The semiconductor structure of claim 9, wherein the metal nitridelayer comprises one of a tantalum nitride layer and a niobium nitridelayer.
 11. A capacitor comprising: a first conductive layer; adielectric layer on the first conductive layer; a second conductivelayer on the dielectric layer; and a crystallized seed layer in at leastone of a first portion of the capacitor between the first conductivelayer and the dielectric layer, and a second portion of capacitorbetween the dielectric layer and the second conductive layer.
 12. Thecapacitor of claim 11, wherein when oxidized, the crystallized seedlayer has a same crystal structure as a crystal structure of thedielectric layer.
 13. The capacitor of claim 12, wherein thecrystallized seed layer comprises a niobium layer and wherein thedielectric layer comprises one of a tantalum oxide layer, a niobiumoxide layer and a composite layer comprising a tantalum oxide layer anda niobium oxide layer.
 14. The capacitor of claim 11, wherein the firstconductive layer and the second conductive layer comprises one of ametal nitride layer, a noble metal layer, a noble metal oxide layer, ametal silicide layer, an impurity-doped silicon layer and a metal layer.15. The capacitor of claim 11, wherein one of the first conductive layerand the second conductive layer is a metal nitride layer that has asimilar crystal structure as a crystal structure of the dielectriclayer.
 16. The capacitor of claim 15, wherein one of the firstconductive layer and the second conductive layer is a niobium nitridelayer or a tantalum nitride layer. 17.-20. (canceled)